Commit Diff

Commit:
1c55ad1b08ae934858f530f9ea3f73a9cf320a00
From:
powerpc64 <powerpc64@localhost>
Date:
Message:
update
Actions:
Patch | Tree
commit - dfac716c3a3daef6ec3e55d6347a1e7906885db6
commit + 1c55ad1b08ae934858f530f9ea3f73a9cf320a00
blob - 4d9dfe31172d8d70d7ff9e4d68a5bfd7db7e0a08
blob + 06b20118d2b0419683cd91c91f23a027a9fdfc11
--- aim64/cpu.c
+++ aim64/cpu.c
@@ -377,22 +377,7 @@ config_l2cr(int cpu)
 	}
 
 	if (l2cr & L2CR_L2E) {
-		if (cpu == PPC_CPU_MPC7450 || cpu == PPC_CPU_MPC7455) {
-			u_int l3cr;
-
-			printf(": 256KB L2 cache");
-
-			l3cr = ppc_mfl3cr();
-			if (l3cr & L3CR_L3E)
-				printf(", %cMB L3 cache",
-				    l3cr & L3CR_L3SIZ ? '2' : '1');
-		} else if (cpu == PPC_CPU_IBM750FX ||
-			   cpu == PPC_CPU_MPC7447A || cpu == PPC_CPU_MPC7457)
-			printf(": 512KB L2 cache");
-		else if (cpu == PPC_CPU_MPC7448)                                                                                                 
-			printf(": 1MB L2 cache");
-		else {
-			switch (l2cr & L2CR_L2SIZ) {
+		switch (l2cr & L2CR_L2SIZ) {
 			case L2SIZ_256K:
 				printf(": 256KB");
 				break;
@@ -405,8 +390,7 @@ config_l2cr(int cpu)
 			default:
 				printf(": unknown size");
 			}
-			printf(" backside cache");
-		}
+		printf(" backside cache");
 #if 0
 		switch (l2cr & L2CR_L2RAM) {
 		case L2RAM_FLOWTHRU_BURST: